Power6: Later in 2007 Rather than Sooner?

April 23, 2007 Timothy Prickett Morgan

There is some hubbub in the server market that IBM‘s Power6 processors have shifted to a later ship date than perhaps Big Blue had planned. It is hard to say for sure exactly what is going on, since IBM does not provide future ship dates for products that are not announced and has vagued up the product roadmaps it shows partners and customers in recent weeks. But IBM’s press relations and top executives have said repeatedly that Power6 will ship in systems in the second half of 2007.

A few months ago, a typo in a press release said it was coming in 2008, and maybe that was what IBM had wished it promised. (If not a Freudian Slip, perhaps it was a Moorean one, since there are more slips in the chip biz than at Victoria’s Secret.) But, at the time, IBM assured everyone that the Power6 chip would be here in 2007. No doubt about it.

And on the conference call with Wall Street analysts yesterday, Mark Loughridge, IBM’s chief financial officer, was asked if there had been any delay in the Power6 products, which will come in System i flavors running i5/OS and System p versions running AIX. The System i machines can also run AIX and Linux in partitions, and the System p machines can run i5/OS and Linux as well, but the machines are really sold with their main operating system with the others being for selected workloads isolated in partitions. IBM does have some traction with Linux-on-Power machines, which have lower prices than AIX System p machine, but this business is very likely dwarfed by even the declining i5/OS business and the much more massive AIX business on the Power-based servers.

“We do see that entering the product line in i and p at the back half of 2007,” Loughridge said. He did not elaborate on when in the back half this might happen. I am working with IBM to try to get someone from the Unix business on the horn to talk a little more specifically about this, and address the rumors out there that Power6 has been delayed any further.

The following roadmap, which IBM was showing customers in Germany in February and March of this year, certainly did not help quell the concerns of customers and partners:

Soon after this roadmap was discovered through the magic of search engines, people started contacting me to see if the subtle changes on the roadmap meant that Power6 was delayed more than it has already been. It is very hard to say, but some other trade rags have made much of this.

The official, public Power processor roadmap, which you can view on the Power.org consortium’s Website at this link, shows Power4 heading off into the sunset at the end of 2003, follow by Power5 coming in early 2004 and Power5+ in mid-2005. Then, in late 2006, up comes Power6. Maybe Power4+ was ignored in this roadmap on purpose, or by accident.

Here’s what the history actually has been so far. The Power4 was the first dual-core processor, and it came to market with much fanfare in October 2001. After some clock speed increases, a Power4+ kicker came out in May 2003, extending the life of the original chip. The Power5 chip started rolling out in the System i5 line in May 2004 and in the System p5 line in July 2004. The p5 line got the Power5+ chip first in selected machines in October 2005, and then the chips appeared in the System i5 products in January 2006 and were rolled out across both lines into the summer. The System p5 line got something that the System i5 line did not get: quad core modules, which pack two Power5+ chips running at a slightly slower clock speed side-by-side in a single package so they can share a socket and so IBM can cram twice as many cores into a “Squadron” server as it would otherwise do. IBM has goosed the clock speeds on the Power5+ chips to satisfy the needs of customers that needed more performance and that cannot wait until Power6 does arrive.

But–and here’s what makes people nervous–the Power5 and Power5+ chips were supposed to scale up through 2.5 GHz and on to 3 GHz and higher according to the roadmaps that came out before the chips did. IBM’s 90 nanometer process ran out of gas. So did Intel’s 65 nanometer process with the dual-core “Montecito” Itanium 9000 processors, which were supposed to hit 2.1 GHz and which run at 1.6 GHz; ditto for the UltraSparc-IV+ chips, which are only now hitting their expected clock speeds and only in very limited volumes.

The roadmap IBM was showing in Germany last month has some interesting tweaks to it. First, the Power5 and Power5+ chips now say 2004 through 2007, when roadmaps before said 2004 through 2006. This is a remarkable change from the nearly continuous 12- to 18-month chip upgrade cycle of the 1990s among the RISC/Unix players, and it shows how performance is not as important as other features these days, such as integrated virtualization and lower power consumption. The implication of this roadmap is that IBM will do 36-month cycles on a chip generation, with an initial and then a kicker iteration. This is not exactly aggressive. The Power6 chip does not say 2006 through 2009, as you would expect it to based on a roadmap circa 2005 or 2007 through 2010, as you would this week given this trend. The “To Come” label is not exactly encouraging, but it does not necessarily mean that Power6 has slipped. Or at least slipped any further than it already has to get into 2007 in the first place.

Power7, which IBM has said very little about, is shown on the roadmap as having an advanced hybrid core design, advanced system features, highly threaded cores, and workload accelerators. This is the first time IBM has said much of anything about Power7, but there are rumors that it will plug into the same cores as Opteron processors from Advanced Micro Devices. If this turns out to be the case, then IBM can do what many System i and System p customers have wanted for years–provide a single system that can run Windows in the same chassis and using the same infrastructure (disk, memory, I/O) as i5/OS, AIX, and Linux. If IBM can’t get Windows ported back to the Power architecture, moving the Power7 chip to a converged X64-Power server design is the next best thing. And it will be interesting to see if this actually happens.

There has been some talk that Power6 chips will come out slower than IBM anticipated, but this roadmap shows the same 3.5 GHz to 5 GHz scaling IBM has talked about at chip shows in recent months. Rather than rely on increasing core count to boost performance, IBM is using the shrink from 90 nanometer to 65 nanometer chip making processes to increase clock speeds, and this may be why IBM’s customers and partners are nervous and competitors are rubbing their hands together with glee.

Sun Microsystems is seeing better traction with its UltraSparc-IV+ chips, which have had their clocks increased to 1.9 GHz and 2.1 GHz in low, controlled volumes, and Fujitsu finally delivering its dual-core Sparc64 VI chips in the new Sparc Enterprise servers (which were announced last week). So IBM has tough competition in the Unix space. Both Sun and Fujitsu are selling the Sparc64 boxes, which can stand toe-to-toe with any Power box IBM can deliver today. Sun is also working on a 16-core, 128-core “Rock” Sparc box for delivery in 2008, which could be a very powerful machine, too. Hewlett-Packard‘s Integrity servers using dual-core “Montecito” Itanium 9000 processors are no slouch, either. (Luckily for everyone but HP, the quad-core “Tukwila” Itaniums, which were supposed to be here in 2007, were pushed out into 2008 way back in October 2005.) And X64 entry and midrange boxes using Xeon or Opteron chips from Intel and AMD can hold their own with Linux, Windows, or Solaris against any p5 or i5 box. The heat is on IBM to deliver with Power6, and the technical specs of the chip show that it has lots of innovations that will be attractive to customers and differentiate it from the pack.

Given past history, it is reasonable to assume that Power6 chips will not come out in all form factors and SMP configurations and across the System i and System p lines all at the same time. It is hard to guess where IBM will deliver first with Power6 chips. But it is safe to assume that the System i5 line will get Power6 first where customer demand will be lowest and profit margins highest, and that means whatever machines follow the i5 570 or 595 boxes to market, which span from four to 64 cores collectively. IBM needs to show top-end performance with the System p line, so you can bet that the kickers to the p5 590s and 595s will see the Power6 chips as soon as possible–and well before the System i line does. And then, if IBM can get slower versions of Power6 chips out the door, maybe running at between 2.5 GHz and 3 GHz, it would be reasonable to ship these in entry rack, entry blade, and midrange rack servers alongside Power5+ variants if Big Blue can’t get volumes out of the chip fabs. After that, you can expect it in the rest of the System i and System p line.

This Issue Sponsored By

Table of Contents

Content archive

Recent Posts

Subscribe

Pages

Search