IBM Goes Vertical with Chip Designs
April 23, 2007 Timothy Prickett Morgan
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When you are trying to limit the distances between any two points, one way you can do that is to move from two to three dimensions and thereby pack things in vertically. This is what humans discovered as they went from caves to homes to McMansions and from towns to cities to megalopolis. So it is only natural that IBM researchers have worked out ways to stack electronic circuits, thereby making the distances between the components shorter. This is important for two big reasons. First, by going 3D with chips, the shorter distances mean that electronic signals can travel faster between independent components in a package of multiple chips. And because the lines are shorter, they use less power. That means electronics suppliers–and IBM is one for its core mainframe and Power systems as well as for embedded devices like game consoles and routers–can do exactly what they have done as they have shrunk the size of transistors along the Moore’s Law curve. They can either crank the speed of the components because electrons do not have to travel so far and therefore do not generate as much heat and experience as much leakage in the circuit, or they can keep the performance relatively constant and make a cooler device. IBM’s Semiconductor Research and Development Center announced last week a new technology with the improbable name of “through-silicon vias” that will allow IBM to take elements of a 2D chip that might be sitting side-by-side relatively far away, like the one in your PC, and stack these chip elements. By stacking the chips and putting wires between silicon layers in the stacked chips to interconnect them, some wire lengths between components can be shortened by a factor of 1,000; moreover, because space is not so tight, the number of electronic channels between components can increase by a factor of 100. This is a big advance, and potentially bigger than the advances from 180 nanometer to 45 nanometer chip technologies in the past decade that has enable so many components to be added to processors. IBM has many things that it is an absolute genius at. One of them is electromechanical engineering. Think of the elegance of a punch card machine, a tape drive, a disk drive, or even an IBM Selectric typewriter, which was a marvelous piece of machinery and arguable the business machine that made it possible for IBM to sell the PC in the first place. The other one is chip making processes and packaging. IBM was the first company to move complex chip assemblies into two dimensions on a large scale with the Thermal Conduction Modules that came out with the 3080 mainframes in 1980. These TCMs could pack up to 130 different chips onto a ceramic substrate with 1,800 I/O pin connectors; the resulting assemblies ran at 300 watts and have water-cooling jackets. Later 3090 mainframes were a little bigger and could burn at 520 watts, and the System/390 CMOS processors used a TCM that could burn at 600 watts, be cooled by air, and pack 121 chips into a single package. The substrate in a TCM had some 3D elements that are the conceptual predecessors to the new 3D techniques, including different layers for signal and power distribution for the multiple chips in the complex. IBM said last week that the through-silicon via 3D chip process is already running in its chip fabs, and that it will start sampling chips using this technology to its customers in the second half of 2007 with production in 2008. The first place IBM will use the technology is in stacking amplifier circuits on wireless LAN and cell phone chips. IBM will also use the process to make new custom Power cores for the Blue Gene/L Power-Linux massively parallel supercomputers, which have hundreds of thousands of processor cores. IBM plans to stack cores on top of cores and memory on top of cores to boost performance and lower power consumption. The company also hinted that its mainstream Power processors would eventually benefit from the technology, allowing IBM to add more cores to the architecture while dropping power usage. RELATED STORIES Will 45 Nanometer Chips Make Two Warring Camps? IBM to Ditch SRAM for Embedded DRAM on Power CPUs IBM, AMD Expect 45-Nanometer Chips in Mid-2008
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