What’s the Story with Power6+ Chips?

May 4, 2009 Timothy Prickett Morgan

As I explained in last week’s issue, I was not surprised that IBM was making server announcements relating to the Power6+ processor. What I didn’t expect to learn was that Big Blue already began the rollout out of Power6+ machines last fall and decided to not tell anyone about it. What good is a kicker if you don’t kick up the clock speeds and brag about new features? This is still the IT industry, right?

For many years now, the i platform folks have been trying to shy away from talking about feeds and speeds and talk about the benefits of the complete system. That’s one tactic to take in marketing, to be sure, but I sometimes get the feeling that the IBMers in charge of sales and marketing forget how long I have been around the midrange and can’t even fathom how long some of the Power Systems i customers have been around.

Since the AS/400 was launched, IBM can–and did–brag about all kinds of nifty technologies that made their first debut inside of AS/400s. In most cases, these technologies–asymmetric multiprocessing, integrated relational database, high-capacity memory chips, RAID 5 data protection, 3.5-inch magnetoresistive head disk drives, the list goes on and on and on–not only made their debut first among IBM machines within an AS/400, but debuted there first in the entire IT industry. The AS/400 might have been conservative and weird, but it was also slick and smart. And the IBM I grew up watching was also the one that created the RAMP-C online transaction processing benchmark test to show that the AS/400 beat the hell out of HP 3000 and DEC VAX minis and was first out the door four years later endorsing the TPC-C benchmark test to prove how good the AS/400s were.

So, to me, when an IT vendor stops talking about the underlying technology they are delivering, it is because that technology is not as competitive as the vendor had hoped. And I have seen it time and time again, not just with the AS/400 and its progeny, but since the late 1990s when Windows went commercial on servers and X86 machinery started beating the tar out of Unix and proprietary minis in their own midrange market.

It is against that decade-long backdrop that I ponder the mysteries of the Power6+ chip, which IBM is still not admitting is out in its announcement letters or in its press releases, but which it most certainly is putting into the new Power 520 and 550 rack and tower servers and the JS23 and JS43 blade servers; last October, the Power6+ was put into the 16-core Power 560 and the 32-core version of the Power 570, too, both of which have two chips (that’s four cores) per processor card.

In explaining IBM’s decision to not talk about Power6+ chips back in October and only admit to it to me because I have been telling people the chip should have been out already, Scott Handy, vice president of marketing and strategy for IBM’s Power Systems division, said it was really quite simple.

“With our sellers, we have been promoting this concept we call performance plus,” Handy explains. “You have to have performance, to be sure, but you also need virtualization, and energy and systems management, and lots of other things–that’s the plus part–to make it all work. We are continuing to take share, and we didn’t need to highlight performance.”

I don’t agree with that, at least not completely, and certainly not in two-socket machines. For one thing, Intel can now cram more cores into a socket than IBM–twice as many–and is delivering a 2U form factor workhorse server while IBM has a very respectable 4U offering in the Power 550 and 560 machines. I think IBM needs faster processors for companies where single thread performance is an issue and that need more cores where applications can take advantage of lots of threads. Intel’s two-core “Nehalem EP” Xeon 5500s, instead of cranking up the clocks, run slower than the four-core variants of the chip. That is idiotic, and it leaves an opening for IBM to put a two-core, four-thread Power6+ chip in the field running at 6 GHz that runs the feet off a Nehalem EP, or Itanium or Opteron or Sparc, for that matter.

But with the Power6+ chips, the clock speed maxes out at 4.7 GHz in the Power 520, 5 GHz in the Power 550, 4.2 GHz in the JS23 and JS43 blades, 3.6 GHz in the double-density Power 560, and 4.2 GHz in the double-density Power 570. The Power6+ does include some tweaks in the 65 nanometer copper/SOI process IBM uses to make the chips, which is why IBM can boost the clock speeds a little over the speeds it could hit with the Power6 generation. Remember, last year the Power 520 only had 4.2 GHz chips, the Power 550 had 3.5 GHz and 4.2 GHz chips, the Power 570 used 3.5 GHz, 4.2 GHz, and 4.7 GHz Power6 chips. (The supercomputing node called the Power 575 crammed 32 Power6 cores running at 4.7 GHz into a 2U chassis, which is quite an accomplishment and which required water cooling.) The high-end Power 595 and its multichip modules came out with cores running at 4.2 GHz and 5 GHz, where they remain today. (MCMs tend to clock a little higher than the single-chip modules used in the Power rack servers.) Basically, a Power6+ running at 3.6 GHz, 4.4 GHz (in the updated Power 570), 4.7 GHz, and 5 GHz is not much different from a Power6 running at 3.5 GHz, 4.2 GHz, and 4.7 GHz. This is nothing to brag about in terms of clock speeds, even if it probably does mean IBM is able to make Power6+ chips more profitably than it could make Power6 chips, given the maturity of the 65 nanometer process.

Handy didn’t address all of the Power roadmap issues I have brought up in the past few weeks, but said that in addition to some tweaks for the Power6+ chips, IBM had at one time planned to save the 5 GHz clock speed for the Power6+ kicker, but the company was able to bring it forward with Power6 in April 2008. And this is one reason why IBM didn’t have as many goodies for Power6+ as it might have otherwise.

Knowing, as you do, that IBM’s original plan for the Power6 and Power6+ chips was to scale from between 4 GHz and 6 GHz and to substantially rework the instruction pipeline to allow that crank all the way up to 6 GHz, you can see also why IBM might not want to talk about Power6+ and its technical challenges. My guess is that the incremental performance creates too much heat, at least with the current 65 nanometer processes used to manufacture the chips. IBM doesn’t provide wattages for its Power family of processors, but at the very least the Power6+ chips ought to run a little cooler now that IBM has been running 65 nanometer in production for almost a year and a half on the Power6 and Power6+ chips.

By the way, the Power6+ chip does have a few different features. According to IBM documentation that I have been able to get my hands on, the Power6 chips had eight memory keys–seven for the operating system kernel and one for the application userspace. The Power6+ chip has eight new memory keys–eight for the kernel, seven for userspaces, and one for the hypervisor, and the new keys, according to this document, “helps prevent accidental memory overwrites that could cause critical applications to crash.” Makes you wonder why Power5, Power5+, or Power6 didn’t have these extra memory keys already, and what is going on out there because they don’t have them. I can understand why IBM might not want to bring these new features up in a press release and have to explain it to a bunch of cranky journalists.

If the eight-core Power7, which is expected in supercomputers later this year for selected customers and in early 2010 for commercial servers, starts to slip, I think we can expect a clock crank on Power6+ in the fall, perhaps in September or October, particularly if the global economy starts to show some signs of life. IBM announced the dual-core Power4 chips into the gaping maw of a recession, and offered two to three times more bang for the buck than competitors in the Unix market and made money hand over fist and ate market share like crazy.

IBM will not be able to make such a leap in 2009 with Power6. Even moving from 5 GHz to 6 GHz will only boost clock speed by 20 percent, and without a balance in the efficiency of chipsets and speed of main memory and cache memory, the extra clocks don’t translate into performance. IBM needs faster DDR2 main memory than the 667 GHz chips it is using, but it is not clear to me that it can boost the speed of memory in the Power Systems line. As memory capacity grows in the Power 570, for instance, the clock speed on the memory has to drop from 667 GHz down to 533 MHz and then to 400 MHz. IBM is playing off memory capacity against memory speed, as other server makers have to do in most of their designs as well. I don’t think Big Blue can do much until it moves to Power7 chips, new chipsets, and 1 GHz, 1.3 GHz, and 1.6 GHz DDR3 main memory.

I would think it was a total hoot if IBM put eight cores on the Power7 chip running at only 3.2 GHz and used 1.6 GHz DDR3 main memory and got memory and clock speeds closer together and made it run more efficiently–like Sun has done with its “Niagara” Sparc T series chips, which run at 1.2 GHz or 1.4 GHz.

We’ll see what happens. It is bound to be interesting.

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