IBM and Partners to Push Chip Tech Down, and Costs, Too

February 22, 2010 Timothy Prickett Morgan

By virtue of its dominance over the global microprocessor market for PCs and servers, Intel is just about the only CPU maker that can afford to do chip design, process design, and wafer baking in its fabs all by its lonesome. Everyone else has to partner, including IBM.

IBM had a slew of partners to push its chip technology to 90 nanometer processors, then down to 65 nanometers, and further tightened to the 45 nanometer tech that is used to make the current eight-core Power7 processors, including customers Sony, Nintendo, and Microsoft, which use variants of the Power architecture in their respective PS3, Wii, and Xbox 360 game consoles; Toshiba also kicked in for research, development, and production tweaking of the processes used to make the “Cell” Power variant, which it uses in HDTV sets and other electronics. IBM and NEC teamed up on chip research and development on 32 nanometer technologies in September 2008, with NEC joining the so-called Fishkill Alliance to push the 32 nanometer envelope along with Chartered Semiconductor (now part of the GlobalFoundries chip baking spin-off of Advanced Micro Devices), Freescale Semiconductor, Infineon Technologies, Samsung Electronics, STMicroelectronics, and Toshiba.

The Fishkill Alliance is looking to perfect the high-k metal gate technology that is being added to the copper/silicon on insulator processes that IBM added to its chips nearly a decade ago. The goal for the alliance partners is to push on down to 22 nanometer processes in the 2011 timeframe and 15 nanometers at some point in the future. The partners work through the Albany NanoTech center, which is operated by the Colleges of Nanoscale Science and Engineering at SUNY Polytechnic Institute; this is the State University of New York (SUNY) campus devoted to engineering, and it just so happens to be about halfway between IBM’s East Fishkill, New York, and Burlington, Vermont, chip fabs.

Last week, IBM tapped Novellus Systems, a maker of chemical deposition equipment used in the etching of chips. Novellus is being brought into the Fishkill Alliance to create better photoresist removal processes. (Photoresist chemicals are used to lay down the areas on a chip where light waves cannot etch away layers of semiconducting material; once the wire patterns are laid down, you have to get rid of the gunk.) IBM and Novellus will work on photoresist stripping processes for 28 nanometer and 22 nanometer wafer baking, including a stripping routine called high dose implant strip (HDIS) that is compatible with high-k metal gate and ultra-low-k dielectric circuits. IBM will be installing the GxT photoresist stripping platform at its East Fishkill fab, and the NanoTech Complex is getting a machine there as well to push the limits. Novellus and the NanoTech Complex had signed a $20 million partnership last July to work on chip tech below the 22 nanometer barrier.

Making smaller chip circuits is not the only thing IBM needs to focus on if it eventually wants to bring Power8 and Power9 processors to market. It also needs to cut the cost of each chip technology leap and improve the yield on its chip making processes.

To that end, IBM Research has joined the Diamond Consortium, a project funded by the European Union to create “a systematic methodology and an integrated environment for the diagnosis and correction of errors” in chip design and manufacturing. The idea is to speed up the design process by making it easier to catch errors long before they end up in silicon, and the way the proposed Diamond system will work is to make a best-guess about where errors will crop up in a design to help chip engineers zero in on where testing should be done. (This sounds suspiciously like letting chips design and test themselves with some nominal human handling, if you like to scare yourself about SkyNet.)

According to the consortium, about 70 percent of the design effort in bringing a new chip to market is focused on verification and debugging of a design; a little less than half of that effort is expended in finding bugs and correcting them. By improving the means through which errors in the chip design are found and corrected, and by adding circuits to deal with various kinds of soft errors (such as those caused by cosmic radiation), the Diamond Consortium cut the time it takes to find and fix faults in half. Time, as John Meynard Keynes proved, is money. How much are we talking? The consortium says that for the average chip design, fault localization and correction costs around $34.5 million, and it eats up time, which in turn lengthens design cycles for each chip.

IBM has not yet said exactly how it might make use of the Diamond Consortium efforts in its own chip making, or what it plans to contribute to the cause.

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