IBM Pushes Power Envelope Down with Power7 Chips
September 7, 2010 Timothy Prickett Morgan
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The IEEE hosted the Hot Chips 22 chip conference at Stanford University while The Four Hundred was on hiatus, and the chipheads who work on IBM‘s Power Systems were on hand to talk about the EnergyScale power-saving features of the new Power7 chip as well as the forthcoming Power7 IH supercomputing node that is part of the petaflops-class “Blue Waters” supercomputer being installed at the University of Illinois. I already told you all that you need to know about the Power Systems IH supercomputer nodes last fall, which is that one of these monsters would have a tremendous amount of CPW power–and you can’t have one. (I do think that some of the underlying hub/switch technologies used in these supercomputing nodes will end up in future Power8 or Power9 systems, and the chip packaging and water-cooling might appear in future Power Systems machines even before then.) If you have a lot of time on your hands, you can read IBM’s presentation on the latest EnergyScale features added to the Power7 chips here. The EnergyScale features were originally part of the Power6 systems, were enhanced a bit with Power6+ machines, and come to fuller fruition with the Power7 boxes. The Power7 chip’s chief architect for the EnergyScale features is Michael Floyd, and he walked everyone through the new features at Hot Chips 22 on August 23. You learn something new every day, and this was the first time I have ever heard of the term “guardbanding,” which just goes to show you how much more I have to learn in this IT racket. When companies design chips and systems, they put some delays in the components so that signals scooting around the guts of the system don’t get stepped on as the system gets busy or hot or as the processor ages. As my colleague at The Register, Rik Myslewski, reported from the Hot Chips 22 conference, this guardbanding has been static in chip designs, but with the Power7 chips, it is dynamic. Which means if the signals are working OK, the slack can be taken back out of the system, allowing it to either run cooler or do more work. How much more work? Well, with the Critical Path Monitor (CPM) feature that does this dynamic guardbanding running, a Power 750 with 32 cores and 64 GB of main memory running the SPECPower_ssj benchmark at full load could be overclocked by 7.3 percent or run 15.8 percent cooler. Those are real numbers. Most IBM i shops don’t give a damn about energy consumption, but extra performance means paying IBM and application software makers less dough and getting more work done in a given amount of time. Myslewski appears to be the only journalist who went to IBM’s Power7 EnergyScale presentation, by the way. (Some days, I wish I lived in San Francisco just so I wouldn’t miss such things.) Floyd also talked about a feature called Low-Activity Detection, or LAD, which figures out when machines are looping, telling system management tools they are busy when they are not really hitting memory at all. In these cases, IBM can drop the clocks by as much as 50 percent, saving loads of juice. Another feature, called a processor core power proxy, allows IBM to guesstimate how much electricity each of the eight cores and their associated L2 cache and L3 cache segments are burning individually without requiring a voltage regulator on each segment. IBM is measuring power consumption all over the chip, chipsets, main memory, and the power proxy assembles this data, creating what is in effect a virtual voltage regulator for each “chiplet,” as IBM calls it, which then feeds data into the Active Energy Manager plug-in for the Systems Director systems management tool. RELATED STORIES IBM slips automatic tranny into Power7 (The Register) The Power7 Chip Gets Some Stiff X64 Competition Brace Yourself For A Bevy Of Server Chip Announcements Power 7: Lots of Cores, Lots of Threads
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